: This article is about the programming utility make. For other articles concerning make, see Make (disambiguation)

make is a utility that automates the process of converting files from one form to another, doing Dependency (computer science) and invoking external programs to do additional work as needed. Its dependency tracking is very simple and centers around the modification time of the input files. Most frequently it is used for compile of source code into object code, joining and then linking object code into executables or libraries. It uses files called makefiles to determine the dependency graph for a given output, and the build scripts which need passed to the shell (computing) to build them. The term makefile stems from their traditional file name of makefile or (later) Makefile .

=Origin=

There are now a number of dependency-tracking build utilities, but make is one of the most wide-spread, primarily due to its inclusion in [http://www.acm.org/awards/ssaward.html Software System Award] for the invention of this important tool.

=Evolution=

Before make s introduction, the Unix build system would most likely consist of make and install shell scripts accompanying a program s source. Being able to combine the commands for the different targets into a single file, and being able to abstract out dependency tracking and archive handling, was an important step in the direction of modern build environments.

make has gone through a number of rewrites, and a number of from-scratch variants which used the same file format and basic algorithmic principles, and also provided a number of their own non-standard enhancements, in the time that followed. The two main variants of the traditional make utility are:

POSIX includes standardization of the basic features and operation of the make utility, and is implemented with varying degrees of completeness in UNIX-based versions of make. In general, simple makefiles may be used between various versions of make with reasonable success. GNU make and BSD make will look first for files named GNUmakefile and BSDmakefile respectively, which allows one to put makefiles which use implementation-defined behaviour in separate locations.

=Usage=

A makefile consists of lines of text which define a file (or set of files) or a rule name as depending on a set of files. Output files are marked as depending on their source files, for example, and source files are marked as depending on files which they include internally. After each dependency is listed, a series of lines of indented text may follow which define how to transform the input into the output, if the former has been modified more recently than the latter. In the case where such definitions are present, they are referred to as build scripts and are passed to the shell to generate the target file. The basic structure is:

# Comments use the pound sign (aka hash) target: dependencies command 1 command 2 . . . command n

A makefile also can contain definitions of variables and inclusion of other makefiles. Variables in makefiles may be overridden in the command line arguments passed to the make utility. This allows users to specify different behaviour for the build scripts and how to invoke programs, among other things. For example, the variable CC is frequently used in makefiles to refer to a C compiler, and the user may wish to provide an alternate compiler to use.

=Advantages and disadvantages=

Like most software which has been around for as long as make has, it has its share of fans and detractors. Many problems have surfaced with scaling make to work with modern, large software projects, some contend, but many also point out that for the common case, make works very well, and has very simple, but powerful, expressiveness. In any event, make is still used for the building of many complete operating systems, and modern replacements are not entirely different in their basic operation.

With the advent of modern Integrated Development Environment, especially on non-UNIX platforms, many programmers do not manually manage dependency tracking, or even the listing of which files are part of a project, and instead leave that task to be automated by their environment. Likewise, many modern programming languages have language-specific ways of listing dependencies which are more efficiently tracked through the use of language-specific build utilities.

=Notable alternatives=

There are also many tools which are like make, but which are not compatible with its makefile format. A comprehensive list is available on the [http://www.a-a-p.org/tools_build.html A-A-P website]. Some of the most notable are: *Apache Ant, which is popular for Java platform development and uses an XML file format. *cook (software), a very powerful tool with a C Programming Language like syntax. *Perforce Jam, which is a generally enhanced, ground-up tool which is similar to make. *Apache Maven, which is very similar to ant. *Mk (Plan 9) - developed originally for Plan 9 (operating system), said to have improved upon make by removing all the vowels from the name , and introducing a completely new syntax that many consider to be easier to read and more powerful. It has been ported to Unix as part of plan9port. *MPW Make -- Developed for Mac OS Classic and loosely similar to but not compatible with Unix make; it was designed with somewhat more complicated dependency syntax to allow for resource files. Mac OS X comes with GNU make. Available as part of the Macintosh Programmer s Workshop as a free, unsupported download from Apple. *[http://search.cpan.org/dist/Module-Build/ Module::Build], which is a Perl module for the building and installation of other Perl modules. It replaces the existing [http://search.cpan.org/dist/ExtUtils-MakeMaker/ ExtUtils::MakeMaker] module, which actually used make to do the building. *NAnt, a tool similar to ant for the .NET framework *SCons, which is based around the Python programming language, and integrates a broader set of features than make. It is based on a Perl build driver called Cons.

=Example Makefile=

Below is a very simple makefile that would compile a source called helloworld.c using cc, a C compiler. The PHONY tag is a technicality that tells make that a particular target name does produce an actual file. The $@ and $< are two of the so-called automatic variables and stand for the target name and so-called implicit source, respectively. There are a number of other automatic variables.

Note that in the clean target, a minus prefixes the command, which tells make to ignore errors in running the command; make will normally exit if execution of a command fails at any point. In the case of a target to cleanup, typically called clean , one wants to remove any files generated by the build process, without exiting if they don t exist. By tagging the clean target PHONY, we prevent make expecting a file to be produced by that target. Note that in this particular case, the minus prefixing the command is redundant in the common case, the -f or force flag to rm will prevent rm exiting due to files not existing. It may exit with an error on other, unintended errors which may be worth stopping the build for.

helloworld: helloworld.o cc -o $@ $< helloworld.o: helloworld.c cc -c -o $@ $< .PHONY: clean clean: -rm -f helloworld helloworld.o

=Criticism=

Though make is a standard tool on Unix platforms, its syntax is notoriously temperamental. It was to be replaced early on in the Unix product cycle but wound up being kept due to a rapid influx of users.

=External links=